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W196
Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
1W196
Features
* Maximized EMI suppression using Cypress's Spread Spectrum Technology * System frequency synthesizer for 440BX, 440ZX, and VIA Apollo Pro-133 * I programmable to 155 MHz (32 selectable frequencies) * Two skew-controlled copies of CPU output * Seven copies of PCI output (synchronous w/CPU output) * One copy of 14.31818-MHz IOAPIC output * One copy of 48-MHz USB output * Selectable 24-/48-MHz clock is determined by resistor straps on power up * One high-drive output buffer that produces a copy of the 14.318-MHz reference * Isolated core VDD pin for noise reduction
2C
............................................................................................... VDDQ2 = 2.5V5% CPU Cycle to Cycle Jitter: ......................................... 250 ps CPU, PCI Output Edge Rate: 1 V/ns CPU0:1 Output Skew: ................................................ 175 ps PCI_F, PCI1:6 Output Skew: ...................................... 500 ps CPU to PCI Skew: ........................1.5 to 4.0 ns (CPU Leads) REF2X/SEL48#, SCLOCK, SDATA: ...............250-k pull-up FS1: ........................................................... 250-k pull-down FS0: .................................................. No pull-up or pull-down Note: Internal pull-up or pull-down resistors should not be relied upon for setting I/O pins HIGH or LOW. Table 1. Pin Selectable Frequency FS1 1 1 0 0 FS0 1 0 1 0 CPU(0:1) 133.3 MHz 105 MHz 100 MHz 66.8 MHz PCI 33.3 MHz 35 MHz 33.3 MHz 33.3 MHz
Key Specifications
Supply Voltages:........................................VDDQ3 = 3.3V5%
Rev 1.0, November 28, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 11
www.SpectraLinear.com
W196
Block Diagram
VDDQ3 REF2X/SEL48# GND X1 X2 XTAL OSC PLL Ref Freq VDDQ3 IOAPIC
Pin Configuration
VDDQ2 CPU0 CPU1 GND
FS1 FS0
PLL 1 /2//3 VDDQ3 PCI_F PCI1 PCI2 PCI3 PCI4
X1 X2 GND PCI_F PCI1 PCI2 PCI3 PCI4 VDDQ3 PCI5 PCI6 VDDQ3 48MHz 24_48MHz/FS1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
GND REF2X/SEL48# VDDQ3 VDDQ2 IOAPIC VDDQ2 CPU0 CPU1 VDDQ3 GND SDATA SCLOCK FS0 GND
SDATA SCLOCK
I2C LOGIC
PCI5 PCI6 GND
VDDQ3 PLL2 48MHz 24_48MHz/FS1 GND
Rev 1.0, November 28, 2006
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W196
Pin Definitions
Pin Name CPU0:1 Pin No. 22, 21 Pin Type O Pin Description CPU Clock Outputs 0 through 1: These two CPU clocks run at a frequency set by FS0:1 or the serial data interface. See Table 1 and Table 5. Output voltage swing is set by the voltage applied to VDDQ2. PCI Bus Clock Outputs 1 through 6 and PCI_F: These seven PCI clock outputs run synchronously to the CPU clock. Voltage swing is set by the power connection to VDDQ3. I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing is set by the power connection to VDDQ2. 48-MHz Output: Fixed 48-MHz USB clock. Output voltage swing is controlled by voltage applied to VDDQ3. 24-MHz or 48-MHz Output/Frequency Select 1 Input: Frequency is set by the state of pin 27 on power-up. This pin doubles as the select strap to determine device operating frequency as described in Table 1. I/O Dual-Function REF2X and SEL48# Pin: Upon power-up, the state of SEL48# is latched. The initial state is set by either a 10K resistor to GND or to VDD. A 10K resistor to GND causes pin 14 to output 48 MHz. If the pin is strapped to VDD, pin 14 will output 2 4MHz. After 2 ms, the pin becomes a high-drive output that produces a copy of 14.318 MHz. Frequency Selection 0 Input: Selects CPU clock frequency as shown in Table 1 on page 1. I2C Data Pin: Data should be presented to this input as described in the I2C section of this data sheet. Internal 250-k pull-up resistor. I2C Clock Pin: The I2C Data clock should be presented to this input as described in the I2C section of this data sheet. Crystal Connection or External Reference Frequency Input: Connect to either a 14.318-MHz crystal or other reference signal. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power Connection: Power supply for core logic and PLL circuitry, PCI, 48/24MHz, and Reference output buffers. Connect to 3.3V supply. Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V supply. Ground Connections: Connect all ground pins to the common system ground plane.
PCI1:6 PCI_F IOAPIC 48MHz 24_48MHz/FS1
5, 6, 7, 8, 10, 11, 4 24 13 14
O
O O I/O
REF2X/SEL48#
27
I/O
FS0 SDATA SCLOCK X1 X2 VDDQ3 VDDQ2 GND
16 18 17 1 2 9, 12, 20, 26 23, 25 3, 15, 19, 28
I I/O I I I P P G
Rev 1.0, November 28, 2006
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W196
Functional Description
I/O Pin Operation Pins 14 and 27 are dual-purpose l/O pins. Upon power-up these pins act as logic inputs, allowing the determination of assigned device functions. A short time after power-up, the logic state of these pins is latched and the pins become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-k "strapping" resistor is connected between the l/O pin and ground or VDD. Connection to ground sets a latch to "0", connection to VDD sets a latch to "1." Figure 1 and Figure 2 show two suggested methods for strapping resistor connections. Upon W196 power-up, the first 2 ms of operation is used for input logic selection. During this period, the REF2X and 24_48MHz clock output buffers are three-stated, allowing the output strapping resistor on the l/O pin to pull the pin and its associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic "0" or "1" condition of the l/O pin is then latched. Next the output buffer is enabled, which converts the l/O pin into an operating clock output. The 2-ms timer is started when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of the clock output is 20 (nominal), which is minimally affected by the 10-k strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When the clock output is enabled following the 2-ms input period, a 14.318-MHz output frequency is delivered on the pin, assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled.
VDD Output Strapping Resistor Series Termination Resistor Clock Load Output Buffer Output Three-state
Q
10 k (Load Option 1) W196 Power-on Reset Timer
Hold Output Low
D
10 k (Load Option 0)
Data Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options Output Strapping Resistor Series Termination Resistor 10 k W196 Power-on Reset Timer Output Buffer Output Three-state
Q
VDD
R Resistor Value R
Clock Load
Hold Output Low
D
Data Latch
Figure 2. Input Logic Selection Through Jumper Option
Rev 1.0, November 28, 2006
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W196
Serial Data Interface
The W196 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W196 initializes with default register settings. Therefore, the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic Table 2. Serial Data Interface Control Functions Summary Control Function Clock Output Disable Description Any individual clock output(s) can be disabled. Disabled outputs are actively held LOW. Provides CPU/PCI frequency selections beyond the selections that are provided by the FS0:1 pins. Frequency is changed in a smooth and controlled fashion. All clock outputs toggle in relation to X1 input, internal PLL is bypassed. Refer to Table 4. Reserved function for future device revision or production device testing. Common Application Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused PCI slots. For alternate microprocessors and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. Production PCB testing. No user application. Register bit must be written as 0. outputs of the chipset. Clock device register changes are normally made upon system initialization, if required. The interface can also be used during system operation for power management functions. Table 2 summarizes the control functions of the serial data interface. Operation Data is written to the W196 in ten bytes of eight bits each. Bytes are written in the order shown in Table 3.
CPU Clock Frequency Selection
Output Three-state Test Mode (Reserved)
Puts all clock outputs into a high-impedance state. Production PCB testing.
Table 3. Byte Writing Sequence Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Commands the W196 to accept the bits in Data Bytes 3-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W196 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the W196, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the W196, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Refer to Cypress SDRAM drivers.
2
Command Code
Don't Care
3
Byte Count
Don't Care
4 5 6 7 8 9 10
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6
Don't Care
Refer to Table 4
The data bits in these bytes set internal W196 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 4, Data Byte Serial Configuration Map.
Rev 1.0, November 28, 2006
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W196
Writing Data Bytes Each bit in the data bytes control a particular device function except for the "reserved" bits which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit 7. Table 4 gives the bit formats for registers located in Data Bytes 3-6. Table 4. Data Bytes 3-6 Serial Configuration Map Affected Pin Bit(s) Pin No. Pin Name Data Byte 3 7 --6 --5 --4 --3 --Bit Control Control Function SEL_3 SEL_2 SEL_1 SEL_0 Frequency Table Selection (Reserved) Bit 1 Bit 0 0 0 0 1 1 0 1 1 0 1 Default 0 0 0 0 0 Table 5 details additional frequency selections that are available through the serial data interface. Table 6 details the select functions for Byte 3, bits 1 and 0.
2 1-0
---
---
Refer to Table 5 Refer to Table 5 Refer to Table 5 Refer to Table 5 Frequency Controlled Frequency Controlled by external FS0:1 pins by BYT3 SEL_(3:0) Table 5 (Table 1) --Function (See Table 6 for function details) Spread Spectrum Off Test Mode Spread Spectrum On (default) All Outputs Three-stated -Low ---Low -Low Low Low Low -Low Low Low Low --Low ---Low Low -Active ---Active -Active Active Active Active -Active Active Active Active --Active ---Active Active
0 10
Data Byte 4 7 6 5 4 3 2 1 0 Data Byte 5 7 6 5 4 3 2 1 0 Data Byte 6 7 6 5 4 3 2 1 0
-14 ---21 -22 4 11 10 8 7 6 5 --24 ---27 27
-24/48MHz ---CPU1 -CPU0 PCI_F PCI6 PCI5 -PCI4 PCI3 PCI2 PCI1 --IOAPIC ---REF2X REF2X
(Reserved) Clock Output Disable (Reserved) (Reserved) (Reserved) Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable (Reserved) (Reserved) Clock Output Disable (Reserved) (Reserved) (Reserved) Clock Output Disable Clock Output Disable
0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0 0 1 0 0 0 1[1] 1[1]
Note: 1. Bits 0 and 1 of Data Byte 6 in Table 4 must be programmed as the same value.
Rev 1.0, November 28, 2006
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W196
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions Data Byte 3, Bit [7:4, 1:0] Bit [1:0] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Bit 7 SEL_3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 6 SEL_2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 5 SEL_1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 4 SEL_0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output Frequency CPU, SDRAM Clocks (MHz) 78 81 113.5 66.8 117 118.5 122 100 126 135 137 138.5 142 144 155 133.3 124 75 83.3 66.8 90 112 95 100 120 115 110 105 140 150 124 133.3 PCI Clocks (MHz) 39 40.5 37.8 33.4 39 39.5 37.3 33.3 31.5 33.75 34.25 34.62 35.5 36 38.75 33.3 41.3 37.5 41.65 33.4 30 37.3 31.67 33.3 40 38.3 36.67 35 35 37.5 31 33.3 If Spread Is On Spread Percentage OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center
Table 6. Select Function for Data Byte 3, Bits 0:1 Input Conditions Data Byte 3 Function Spread Spectrum OFF Test Mode Spread Spectrum ON (default) Three-state Bit 1 0 0 1 1 Bit 0 0 1 0 1 CPU0:1 Note 2 X1/2 0.5% Hi-Z PCI_F, PCI1:6 Note 2 CPU/2, 3, or 4 0.5% Hi-Z Output Conditions REF2X, IOAPIC 14.318 MHz X1 14.318 MHz Hi-Z 48MHZ 48 MHz X1/2 48 MHz Hi-Z 24MHZ 24 MHz X1/4 24 MHz Hi-Z
Note: 2. CPU and PCI frequency selections are listed in Table 1 and Table 5.
Rev 1.0, November 28, 2006
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W196
Absolute Maximum Ratings[3]
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condiParameter VDD, VIN TSTG TA TB ESDPROT Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Input ESD Protection tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 2 (min.) Unit V C C C kV
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5%
Parameter Supply Current IDDQ3 IDDQ3 Logic Inputs VIL VIH IIL IIH VOL VOH VOH IOL Input Low Voltage Input High Voltage Input Low Current[5] Input High Current[5] Output Low Voltage Output High Voltage Output High Voltage Output Low Current CPU0:1/IOAPIC CPU0:1 PCI_F, PCI1:6 IOAPIC REF2X 48MHz, 24MHz IOH Output High Current CPU0:1 PCI_F, PCI1:6 IOAPIC REF2X 48MHz, 24MHz Crystal Oscillator VTH CLOAD CIN,X1 X1 Input Threshold Voltage[6] Load Capacitance, as seen by External Crystal[7] X1 Input Capacitance[8] Pin X2 unconnected VDDQ3 = 3.3V 1.65 14 28 V pF pF IOL = 1 mA IOH = -1 mA IOH = -1 mA VOL = 1.25V VOL = 1.5V VOL = 1.25V VOL = 1.5V VOL = 1.5V VOL = 1.25V VOL = 1.5V VOL = 1.25V VOL = 1.5V VOL = 1.5V 3.1 2.2 45 85 65 110 50 35 60 45 100 50 60 110 90 140 70 50 95 87 130 70 80 140 140 170 90 80 130 140 150 90 GND - 0.3 2.0 0.8 VDD + 0.3 -25 10 50 V V A A mV V V mA mA mA mA mA mA mA mA mA mA Combined 3.3V Supply Current Combined 2.5V Supply Current CPU0:1 =100 MHz Outputs Loaded[4] CPU0:1 =100 MHz Outputs Loaded[4] 85 30 mA mA Description Test Condition Min. Typ. Max. Unit
Clock Outputs
Rev 1.0, November 28, 2006
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W196
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5% (continued)
Parameter Description Test Condition Min. Typ. Max. Unit
Notes: 3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required 4. 5. 6. 7. All clock outputs loaded with maximum lump capacitance test load specified in the AC Electrical Characteristics section. W196 logic inputs have internal pull-up resistors, except SEL100/66# (pull-ups not full CMOS level). X1 input threshold voltage (typical) is VDD/2. The W196 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
Pin Capacitance/Inductance CIN COUT LIN Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Except X1 and X2 5 6 7 pF pF nH
AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%,VDDQ2 = 2.5V 5%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled. CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20 pF) CPU = 66.8 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.25V Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 20 15 5.2 5.0 1 1 45 4 4 55 200 15.5 CPU = 100 MHz Typ. Max. Unit 10.5 ns ns ns 4 4 55 250 V/ns V/ns % ps 10 3.0 2.8 1 1 45 Min. Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.0V
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance
175 3
175 3
ps ms
Zo
20
Rev 1.0, November 28, 2006
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W196
PCI Clock Outputs, PCI1:6 and PCI_F (Lump Capacitance Test Load = 30 pF CPU = 66.8/100 MHz Parameter tP tH tL tR tF tD tJC tSK tO fST Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew CPU to PCI Clock Skew Description Test Condition/Comments Measured on rising edge at 1.5V Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. 1 Min. 30 12 12 1 1 45 4 4 55 250 500 4 3 Typ. Max. Unit ns ns ns V/ns V/ns % ps ps ns ms
Frequency Stabilization Assumes full supply voltage reached within 1 ms from Power-up (cold start) from power-up. Short cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. 20
Zo
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.8/100 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.0V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 15 1 1 45 Min. Typ. 14.31818 4 4 55 1.5 Max. Unit MHz V/ns V/ns % ms
Zo
REF2X Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.8/100 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 15 0.5 0.5 45 Min. Typ. 14.318 2 2 55 3 Max. Unit MHz V/ns V/ns % ms
Zo
Rev 1.0, November 28, 2006
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W196
48-MHZ and 24-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (48.008 - 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 25 0.5 0.5 45 Min. Typ. 48.008 24.004 +167 57/17, 57/34 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm
Zo
Ordering Information
Ordering Code W196 Package Name G Package Type 28-pin SOIC (300 mils)
Package Diagram
DIMENSIONS IN INCHES[MM]
PART # S28.4 STANDARD PKG. SZ28.4 LEAD FREE PKG.
MIN. MAX.
28-Lead (400-Mil) Molded SOIC S28
DETAIL
A
PIN 1 ID
EXTERNAL LEAD DESIGN
14
1
.395[10.033] .405[10.287] .530[13.462] .545[13.843] .013[0.330] .019[0.482] .026[0.660] .032[0.812] .015[0.381] .020[0.508]
15
28
OPTION 1
SEATING PLANE .720[18.288] .730[18.542]
OPTION 2
.090[2.286] .109[2.768]
.050[1.270] TYP.
A
.002[0.050] .014[0.355]
0.004[0.102] .015[0.381] .050[1.270] .007[0.177] .013[0.330]
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 28, 2006
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